M.Tech. Electronics 2nd Sem Syllabus

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Multimedia Communication
Subject Code : 14ECS254

IA Marks : 50
No. of Lecture Hours /week : 04 Exam Hours : 03
Total no. of Lecture Hours : 50 Exam Marks : 100

Multimedia Communications: multimedia information representation, multimedia networks, multimedia applications, network QoS and application QoS.
Information Representation: text, images, audio and video, Text and image compression, compression principles, text compression, image
compression. Audio and video compression, audio compression, video compression, video compression principles, video compression standards:
H.261, H.263, P1.323, MPEG 1, MPEG 2, Other coding formats for text, speech, image and video.


Detailed Study of MPEG 4: coding of audiovisual objects, MPEG 4 systems, MPEG 4 audio and video, profiles and levels. MPEG 7
standardization process of multimedia content description, MPEG 21 multimedia framework, Significant features of JPEG 2000, MPEG 4
transport across the Internet.
Synchronization: notion of synchronization, presentation requirements, reference model for synchronization, Introduction to SMIL, Multimedia
operating systems, Resource management, process management techniques.
Multimedia Communication Across Networks: Layered video coding, error resilient video coding techniques, multimedia transport across IP
networks and relevant protocols such as RSVP, RTP, RTCP, DVMRP, multimedia in mobile networks, multimedia in broadcast networks.

Reference Books:
1. Fred Halsall, “Multimedia Communications”, Pearson education, 2001
2. K. R. Rao, Zoran S. Bojkovic, Dragorad A. Milovanovic, “Multimedia Communication Systems”, Pearson education, 2004
3. Raif steinmetz, Klara Nahrstedt, “Multimedia: Computing, Communications and applications”, Pearson education, 2002
4. Tay Vaughan, “Multimedia: Making it work”, 6th edition, Tata McGraw Hill, 2004
5. John Billamil, Louis Molina, “Multimedia: An Introduction”, PHI, 2002
6. Pallapa Venkataram, “Multimedia Information Systems”, Pearson education (In Press), 2005

Coding Theory
Subject Code : 14ELD22

IA Marks : 50
No. of Lecture Hours /week : 04 Exam Hours : 03
Total no. of Lecture Hours : 50 Exam Marks : 100

Information and Entropy: Sources of information, DMS and Markov. Properties of Entropy. Entropy of information sources, Extension of a DMS.
Information channels, probability relations in a channel, A Priori, A Posteriori Entropies, Equivocation, Mutual information, Capacity of BSC,
BEC, Noiseless and deterministic channels.
Source coding: Uniquely EL Dodable codes, Instantaneous codes and its construction, Average length of a code, Bounds for Average
Length,Kraft’sInequality. R-ary compact codes. Code efficiency, Redundancy. Shannon-Fano and Huffman code.
Algebra: Groups, rings and fields, properties of finite fields, Galois field arithmetic and its realization, Vector spaces, Matrices.
Channel Coding: Block codes, Minimum distance of a block code, Singleton bound. Performance of Codes. Hamming codes. Cyclic codes, Golay
Codes BCH codes, R-S codes. Convolutional codes. Viterbi Algorithm. LDPC Codes.

Reference Books:
1. S. Lin and D. J. Costello Jr, “Error Control Coding”, Pearson Prentice Hall, 2004
2. T. K. Moon, “Error Correction Coding: Mathematical Methods And Algorithms”, Student Edition, John Wiley & Sons, 2005

Digital Signal Compression
Subject Code : 14ELD23

IA Marks : 50
No. of Lecture Hours /week : 04 Exam Hours : 03
Total no. of Lecture Hours : 50 Exam Marks : 100

Introduction: Compression techniques, Modeling & coding, Distortion criteria, Differential Entropy, Rate Distortion Theory, Vector Spaces,
Information theory, Models for sources, Coding – uniquely ELDodable codes, Prefix codes, Kraft McMillan Inequality
Quantization: Quantization problem, Uniform Quantizer, Adaptive Quantization, Non-uniform Quantization; Entropy coded Quantization, Vector
Quantization, LBG algorithm, Tree structured VQ, Structured VQ, Variations of VQ – Gain shape VQ, Mean removed VQ, Classified VQ,
Multistage VQ, Adaptive VQ, Trellis coded quantization
Differential Encoding: Basic algorithm, Prediction in DPCM, Adaptive DPCM, Delta Modulation, Speech coding – G.726, Image coding.
Transform Coding: Transforms – KLT, DCT, DST, DWHT; Quantization and coding of transform coefficients, Application to Image
compression – JPEG, Application to audio compression.
Sub-band Coding: Filters, Sub-band coding algorithm, Design of filter banks, Perfect reconstruction using two channel filter banks, M-band
QMF filter banks, Poly-phase ELDomposition, Bit allocation, Speech coding – G.722, Audio coding – MPEG audio, Image compression
Wavelet Based Compression: Wavelets, Multiresolution analysis & scaling function, Implementation using filters, Image compression – EZW,
SPIHT, JPEG 2000
Analysis/Synthesis Schemes: Speech compression – LPC-10, CELP, MELP, Image Compression – Fractal compression
Video Compression: Motion compensation, Video signal representation, Algorithms for video conferencing & videophones – H.261, H. 263,
Asymmetric applications – MPEG 1, MPEG 2, MPEG 4, MPEG 7, Packet video
Lossless Coding: Huffman coding, Adaptive Huffman coding, Golomb codes, Rice codes, Tunstall codes, Applications of Huffman coding,
Arithmetic coding, Algorithm implementation, Applications of Arithmetic coding, Dictionary techniques – LZ77, LZ78, Applications of LZ78 –
JBIG, JBIG2, Predictive coding – Prediction with partial match, Burrows Wheeler Transform, Applications – CALIC, JPEG-LS, Facsimile coding
– T.4, T.6.

Reference Books:
1. K. Sayood, “Introduction to Data Compression,” Harcourt India Pvt. Ltd. & Morgan Kaufmann Publishers, 1996.
2. N. Jayant and P. Noll, “Digital Coding of Waveforms: Principles and Applications to Speech and Video,” Prentice Hall, USA, 1984.
3. D. Salomon, “Data Compression: The Complete Reference”, Springer, 2000.
4. Z. Li and M.S. Drew, “Fundamentals of Multimedia,” Pearson Education (Asia) Pte. Ltd., 2004.

Real Time Operating Systems
Subject Code : 14ELD24

IA Marks : 50
No. of Lecture Hours /week : 04 Exam Hours : 03
Total no. of Lecture Hours : 50 Exam Marks : 100

Introduction to Real-Time Embedded Systems: Brief history of Real Time Systems, A brief history of Embedded Systems.
System Resources: Resource Analysis, Real-Time Service Utility, Scheduling Classes, The Cyclic Executive, Scheduler Concepts, Preemptive
Fixed Priority Scheduling Policies, Real-Time OS, Thread Safe Reentrant Functions.
Processing: Preemptive Fixed-Priority Policy, Feasibility, Rate Montonicleast upper bound, Necessary and Sufficient feasibility, Deadline –
Monotonic Policy, Dynamic priority policies.
I/O Resources: Worst-case Execution time, Intermediate I/O, Execution efficiency, I/O Architecture.
Memory: Physical hierarchy, Capacity and allocation, Shared Memory, ECC Memory, Flash file systems.
Multi-resource Services: Blocking, Deadlock and livestock, Critical sections to protect shared resources, priority inversion.
Soft Real-Time Services: Missed Deadlines, QoS, Alternatives to rate monotonic policy, Mixed hard and soft real-time services.
Embedded System Components: Firmware components, RTOS system software mechanisms, Software application components.
Debugging Components: Exceptions assert, Checking return codes, Single-step debugging, kernel scheduler traces, Test access ports, Trace
ports, Power-On self test and diagnostics, External test equipment, Application-level debugging.
Performance Tuning: Basic concepts of drill-down tuning, hardware – supported profiling and tracing, Building performance monitoring into
software, Path length, Efficiency, and Call frequency, Fundamental optimizations.
High availability and Reliability Design: Reliability and Availability, Similarities and differences, Reliability, Reliable software, Available
software, Design tradeoffs, Hierarchical applications for Fail-safe design.
Design of RTOS – PIC microcontroller. (Chap 13 of book MykePredko)

Reference Books:
1. Sam Siewert, “Real-Time Embedded Systems and Components”, Cengage Learning India Edition, 2007.
2. MykePredko, “Programming and Customizing the PIC microcontroller”, 3rd Ed, TMH, 2008.
3. Dreamtech Software Team, “Programming for Embedded Systems”, Jhon Wiley, India Pvt. Ltd., 2008.

VLSI Design and Verification
Subject Code : 14ELD251

IA Marks : 50
No. of Lecture Hours /week : 04 Exam Hours : 03
Total no. of Lecture Hours : 50 Exam Marks : 100

Note: Today, the complexity of the VLSI integrated circuits that are being designed is so large that pre-silicon verification presents a major challenge to the design team. The fact that IP from multiple sources are integrated todayto create a system-on-chip design further complicates the matter. Simulationbased verification techniques that were developed in the past are considered inadequate to-day, since they require too many test cases and require too much development time and run-time. Raising the level of abstraction to design can help bring down the simulation cost. Formal specification and verification techniques are another way to address the challenge of design verification.
Importance of Design Verification: What is verification? What is attest bench? The importance of verification, Reconvergence model, Formal
verification, Equivalence checking, Model checking, Functional verification.[Ref1- Chapter1]
Functional verification approaches: Black box verification, white box verification, grey box verification. Testing versus verification: scan
based testing, design for verification. Verification reuse. The cost of verification.[Ref1- Chapter1]
Verification Tools: Linting tools: Limitations of linting tools, linting verilog source code, linting VHDL source code, linting OpenVera and esource
code, code reviews. Simulators: Stimulus and response, Event based simulation, cycle based simulation, Co-simulators, verification
intellectual property: hardware modelers, waveform viewers.[Ref1-Chapter2]
Code Coverage: statement coverage, path coverage, expression coverage, FSM coverage, what does 100%coverage mean? Functional coverage:
Item Coverage, cross coverage, Transition coverage , what does 100% functional mean? Verification languages: Assertions: simulation based
assertions, formal assertions proving. Metrics: Code related metrics, Quality related metrics, interpreting metrics.[Ref1-Chapter2]
The verification plan: The role of verification plan: specifying the verification plan, defining the first success. Levels of verification: unit level
verification, reusable components verification, ASIC and FPGA verification, system level verification, board level verification, verifying
strategies, verifying responses. [Ref1-Chapter3]
From specification to features: component level feature, system level features, Error types to look for?, prioritise, design for verification.
Directed test bench approaches group into test cases, from test cases to test benches, measuring progress. Coverage driven random based
approach: Measuring progress, From features to functional coverage, from features to test bench, From features to generators, directed test cases.
[Ref1-Chapter3]
Static Timing Verification: Concept of static timing analysis. Cross talk and noise. Limitations of STA. slew of a wave form, Skew between the
signals, Timing arcs and unateness, Min and Max timing paths, clock domains, operating conditions, critical path analysis, falsepaths, Timing
models. [Ref2 Chapter 1, 2, 3, 8]
Physical Design Verification: Layout rule checks and electrical rule checks. Parasitic extraction. Antenna, Crosstalk and Noise: Cross talk
glitch analysis, crosstalk delayanalysis, timing verification [Ref4 Chapter 8]
IP-Reuse in modern-day SoC: SoC Integration and the problem of verification of IP-based designs. Verification IP and their importance,
Formal Verification: SAT BDDs, Symbolic Model Checking with BDDs, Model Checking using SAT, Equivalence Checking. [Ref 5, Ref3
Chapter 1, 2]

Reference Books:
1. JanickBergeron, “Writing testbenches: functional verification of HDL models”, 2nd edition ,Kluwer Academic Publishers,2003
2. JayaramBhasker,RakeshChadha ,“Static Timing Analysis for Nanometer Designs” A practical approach, Springer publications
3. S.Minato “Binary Decision diagram and applications for VLSICAD”, Kulwer Academic pub November 1996
4. PrakashRashinkar, PeterPaterson,Leena Singh “System on a Chip Verification”, Kulwer Publications.
5. http://www.cse.psu.edu/~vijay/verify/instructors.html

Synthesis and Optimization of Digital Circuits
Subject Code : 14ELD252

IA Marks : 50
No. of Lecture Hours /week : 04 Exam Hours : 03
Total no. of Lecture Hours : 50 Exam Marks : 100

Introduction: Microelectronics, semiconductor technologies and circuit taxonomy, Microelectronic design styles, computer aided synthesis and optimization.
Graphs: Notation, undirected graphs, directed graphs, combinatorial optimization, Algorithms, tractable and intractable problems, algorithms
for linear and integer programs, graph optimization problems and algorithms, Boolean algebra and Applications.
Hardware Modeling: Hardware Modeling Languages, distinctive features, structural hardware language, Behavioural hardware language,
HDLs used in synthesis, abstract models, structures logic networks, state diagrams, dataflow and sequencing graphs, compilation and
optimization techniques.
Two Level Combinational Logic Optimization: Logic optimization, principles, operation on two level logic covers, algorithms for logic
minimization, symbolic minimization and encoding property, minimization of Boolean relations.
Multiple Level Combinational Optimizations: Models and transformations for combinational networks, algebraic model, Synthesis of testable
network, algorithm for delay evaluation and optimization, rule based system for logic optimization.
Sequential Circuit Optimization: Sequential circuit optimization using state based models, sequential circuit optimization using network models.
Schedule Algorithms: A model for scheduling problems, Scheduling wither source and without resource constraints, Scheduling algorithms for extended sequencing models, Scheduling Pipe lined circuits.
Cell Library Binding: Problem formulation and analysis, algorithms for library binding, specific problems and algorithms for library binding
(lookup table F.P.G.As and Anti fuse based F.P.G.As), rule based library binding.
Testing: Simulation, Types of simulators, basic components of a simulator, fault simulation Techniques, Automatic test pattern generation
methods (ATPG), design for Testability (DFT) Techniques.

Reference Books:
1. Giovanni De Micheli, “Synthesis and Optimization of Digital Circuits”, Tata McGraw-Hill, 2003.
2. SrinivasDevadas, AbhijitGhosh, and Kurt Keutzer, “Logic Synthesis”, McGraw-Hill, USA, 1994.
3. NeilWeste and K. Eshragian, “Principles of CMOS VLSI Design: A System Perspective”, 2nd edition, Pearson Education (Asia) Pte. Ltd., 2000.
4. KevinSkahill, “VHDL for Programmable Logic”, Pearson Education(Asia) Pvt. Ltd., 2000

MEMS
Subject Code : 14ELD253

IA Marks : 50
No. of Lecture Hours /week : 04 Exam Hours : 03
Total no. of Lecture Hours : 50 Exam Marks : 100

Overview of MEMS & Microsystems: MEMS & Microsystems, Typical MEMS and Micro system products — features of MEMS, The
multidisciplinary nature of Microsystems design and manufacture, Applications of Microsystems in automotive industry, health care industry,
aerospace industry, industrial products, consumer products and telecommunications.
Scaling Laws in Miniaturization: Introduction to scaling, scaling in geometry, scaling in rigid body dynamics, scaling electrostatic forces,
electromagnetic forces, electricity, scaling in fluid mechanics & heat transfer.
Transduction Principles in MEMS & Microsystems: Introduction, Micro sensors — thermal, radiation, mechanical, magnetic and bio —
sensors, Micro actuation, MEMS with micro actuators.
Microsystems Fabrication Process: Introduction, Photolithography, Ion-implantation, diffusion, oxidation, CVD, PVD, etching and materials
used for MEMS, Some MEMS fabrication processes: surface micro-machining, bulk micromachining, LIGA process, LASER micro
machining, MUMPS, FAB-less fabrication.
Micro System Design and Modeling: Introduction, Design considerations: Process design, Mechanical design, Modeling using CAD tools:
ANSYS / Multiphysics or Intellisuite or MEMS CAD, Features and Design considerations of RF MEMS, Design considerations of Optical
MEMS (MOEMS), Design and Modeling: case studies – i) Cantilever beam ii) Micro switches iii) MEMS based SMART antenna in mobile
applications for maximum reception of signal in changing communication conditions and iv) MEMS based micro mirror array for control and
switching in optical communications.
Micro system packaging: Over view of mechanical packaging of micro electronics micro system packaging, Interfaces in micro system
packaging, Packaging technologies.

Reference Books:
1. Tai Ran Hsu, “MEMS and Micro Systems : Design and Manufacture”, Tata McGraw Hill, 2002
2. Boca Raton, “MEMS and NEMS: Systems, Devices and Structures”, CRC Press, 2002
3. J. W. Gardner and V. K. Vardan, “Micro Sensors MEMS and SMART Devices”, John Wiley, 2002
4. N. Maluf, “Introduction to Micro Mechanical Systems Engineering, Artech House”, Norwood, MA, 2000.

Modern DSP
Subject Code : 14ELD21

IA Marks : 50
No. of Lecture Hours /week : 04 Exam Hours : 03
Total no. of Lecture Hours : 50 Exam Marks : 100

Goal of the course – Advances in Digital Signal Processing involve variable sampling rates and thus the multirate signal processing and hence
their applications in communication systems and signal processing. It is intended to introduce a basic course in multirate signal processing
especially meant for students of branches eligible for M Tech courses in EC related disciplines.
Introduction and Discrete Fourier Transforms: Signals, Systems and Processing, Classification of Signals, The Concept of Frequency in
Continuous-Time and Discrete-Time Signals, Analog-to-Digital and Digital-to-Analog Conversion, Frequency-Domain Sampling: The Discrete
Fourier Transform, Properties of the DFT, Linear Filtering Methods Based on the DFT (Ref.1 Chap. 1 & 7)
Design of Digital Filters: General Considerations, Design of FIR Filters, Design of IIR Filters from Analog Filters, Frequency Transformations.
(Ref.1Chap.10)
Multirate Digital Signal Processing: Introduction, EL Dimation by a factor ‘D’, Interpolation by a factor ‘I’, Sampling rate Conversion by a
factor ‘I/D’, implementation of Sampling rate conversion, Multistage implementation of Sampling rate conversion, Sampling rate conversion of Band Pass Signals, Sampling rate conversion by an arbitrary factor, Applications of Multirate Signal Processing, Digital Filter banks, Two Channel Quadrature Mirror Filter banks, M-Channel QMF bank. (Ref.1 Chap.11)
Adaptive Filters: Applications of Adaptive Filters, Adaptive Direct Form FIR Filters- The LMS Algorithm, Adaptive Direct Form Filters-RLS Algorithm. (Ref.1 Chap.13)

Reference Books:
1. Proakis and Manolakis, “Digital Signal Processing”, Prentice Hall 1996. (Fourth Edition).
2. Roberto Cristi, “Modern Digital Signal Processing”, Cengage Publishers, India, (Erstwhile Thompson Publications), 2003.
3. S.K. Mitra, “Digital Signal Processing: A Computer Based Approach”, III Ed, Tata McGraw Hill, India, 2007.
4. E.C. Ifeachor and B W Jarvis, “Digital Signal Processing, a practitioners approach,” II Edition, Pearson Education, India, 2002 Reprint.

Spread Spectrum Communication
Subject Code : 14ECS255

IA Marks : 50
No. of Lecture Hours /week : 04 Exam Hours : 03
Total no. of Lecture Hours : 50 Exam Marks : 100

Review of digital communication concepts, direct sequence and frequency hop spread spectrum systems.
Hybrid direct sequence/frequency hop spread spectrum. Complex envelop representation of spread spectrum signals.
Sequence generator fundamentals, Maximum length sequences. Gold and Kasami codes, Nonlinear Code generators.
Spread spectrum communication system model, Performance of spread spectrum signals in jamming environments, Performance of spread
spectrum communication systems with and without forward error correction.
Diversity reception in fading channels, Cellular radio concept, CDMA cellular systems. Examples of CDMA cellular systems. Multicarrier
CDMA systems. CDMA standards

Reference Books:
1. R. L. Peterson, R. E. Zeimer and D. E. Borth, “Introduction to Spread Spectrum Communications”, Pearson, 1995.
2. J. D. Proakis and M. Salehi, “Digital Communication”, McGraw Hill, 2008
3. A. J. Viterbi, “CDMA: Principles of Spread Spectrum Communications”, Addision Wesley, 1995.
4. S. Verdu, “Multiuser Detection”, Cambridge University Press, 1998

Digital Electronics Lab -2
Subject Code : 14ELD26

IA Marks : 50
No. of Lecture Hours /week : 03 Exam Hours : 03
Total no. of Lecture Hours : 42 Exam Marks : 100

Graphical Programming using LabVIEW
Design of 4 bit Adders (CLA, CSA, CMA, Parallel adders)
Design of Binary Subtractors
Design of Encoder (8X3), ELDoder(3X8)
Design of Multiplexer (8X1), and Demultiplexer (1X8)
Design of code converters & Comparator
Design of FF (SR, D, T, JK, and Master Slave with delays)
Design of registers using latches and flip-flops
Design of 8 bit Shift registers
Design of Asynchronous & Synchronous Counters
ARM-CORTEX M3
[Programming to be done using Keiluvision 4 and download the program on to a M3 evaluation board such as NXP LPC1768 or
ATMEL ATSAM3U].
Write an Assembly language program to calculate 10+9+8+………+1
Write a Assembly language program to link Multiple object files and link them together.
Write a Assembly language program to store data in RAM.
Write a C program to Output the “Hello World” message using UART.
Write a C program to Design a Stopwatch using interrupts.
Write an Exception vector table in C
Write an Assembly Language Program for locking a Mutex.
Write a SVC handler in C. Use the wrapper code to extract the correct stack frame starting location. The C handler can then use this to extract
the stacked PC location and the stacked register values.

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