M.Tech. Electronics 1st Semester Syllabus

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Simulation Modelling and Analysis
Subject Code : 14ELD155

IA Marks : 50
No. of Lecture Hours /week : 04 Exam Hours : 03
Total no. of Lecture Hours : 50 Exam Marks : 100

Basic simulation modeling: nature of simulation, system models, discrete event simulation, single server simulation, alternative approaches, other types of simulation.
Building valid, credible and detailed simulation models. Techniques for increasing model validity and credibility, comparing real world observations
Selecting input probability distributions. Useful probability distributions, assessing sample independence, activity I, II and III. Models of arrival process.


Random numbers generators: linear congruential, other kinds, testing random number generators. Random variate generation: approaches, continuous random variates, discrete random variates, correlated random variates.
Output data analysis. Statistical analysis for terminating simulations, analysis for steady state parameters. Comparing alternative system configurations. Confidence intervals. Variance reduction techniques. Antithetic and Control variates.

Reference Books:
1. Jerry Banks, “Discrete event system simulation”, Pearson, 2009
2. Averill Law “Simulation modeling and analysis”, MGH 4th edition, 2007
3. Seila, Ceric, Tadikamalla, “Applied simulation modeling”, Cengage, 2009.
4. George S. Fishman, “Discrete event simulation”, Springer, 2001
5. N. Viswanadham, Y. Narahari, “Performance modeling of automated manufacturing systems”, PHI, 2000
6. Frank L. Severance, “System modeling and simulation”, Wiley, 2009
7. K. S. Trivedi, “Probability and stastistics with reliability queuing and computer science applications”, PHI, 2007.

Digital VLSI Design
Subject Code : 14EVE12

IA Marks : 50
No. of Lecture Hours /week : 04 Exam Hours : 03
Total no. of Lecture Hours : 50 Exam Marks : 100

MOS Transistor: The Metal Oxide Semiconductor (MOS) Structure, The MOS System under External Bias, Structure and Operation of
MOS Transistor, MOSFET Current-Voltage Characteristics, MOSFET Scaling and Small-Geometry Effects.
MOS Inverters: Static Characteristics: Introduction, Resistive-Load Inverter, Inverters with n_Type MOSFET Load, CMOS Inverter.
MOS Inverters: Switching Characteristics and Interconnect Effects: Introduction, Delay-Time Definition, Calculation of Delay Times,
Inverter Design with Delay Constraints, Esimation of Interconnect Parasitics, Calculation of Interconnect Delay, Switching Power
Dissipation of CMOS Inverters.
Dynamic Logic Circuits : Introduction, Basic Principles of Pass Transistor Circuits, Voltage Bootstrapping, Synchronous Dynamic
Circuit Techniques, Dynamic CMOS Circuit Techniques, High Performance Dynamic CMOS Circuits.
Semiconductor Memories: Introduction, Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM),
Nonvolatile Memory, Flash Memory, Ferroelectric Random Access Memory (FRAM).
Low-Power CMOS Logic Circuits: Introduction, Overview of Power Consumption, Low-Power Design Through Voltage Scaling,
Estimation and Optimization of Switching Acivity, Reduction of Switched Capacitance, Adiabatic Logic Circuits.
BiCMOS Logic Circuits: Introduction, Bipolar Junction Transistor (BJT): Structure and Operation, Dynamic Behavior of BJTs, Basic
BiCMOS Circuits: Static Behavior, Switching Delay in BiCMOS Logic Circuits, BiCMOS Applications.
Chip Input and Output ( I/O ) Circuits: Introduction, ESD Protection, Input Circuits, Output Circuits and L(di/dt) Noise, On-Chip Clock
Generation and Distribution, Latch-Up and Its Prevention.
Design for Manufacturability : Introduction, Process Variations, Basic Concepts and Definitions, Design of Experiments and
Performance Modelling, Parametric Yield Esimation, Parametric Yield Maximization, Worst-Case Analysis, Performance Variability Minimization.

Reference Books:
1. Sung Mo Kang & Yosuf Leblebici, “CMOS Digital Integrated Circuits: Analysis and Design”, Tata McGraw-Hill, Third Edition.
2. Neil Weste and K. Eshragian, “Principles of CMOS VLSI Design: A System Perspective”, Second Edition, Pearson Education (Asia) Pvt. Ltd. 2000.

Advanced Embedded Systems
Subject Code : 14EVE13

IA Marks : 50
No. of Lecture Hours /week : 04 Exam Hours : 03
Total no. of Lecture Hours : 50 Exam Marks : 100

Typical Embedded System: Core of the Embedded System, Memory, Sensors and Actuators, Communication Interface, Embedded Firmware, Other System Components.
Characteristics and Quality Attributes of Embedded Systems: Hardware Software Co-Design and Program Modeling: Fundamental Issues in Hardware Software Co-Design, Computational Models in Embedded Design, Introduction to Unified Modeling Language, Hardware Software Trade-offs.
Embedded Hardware Design and Development :EDA Tools, How to Use EDA Tool, Schematic Design – Place wire, Bus , port, junction,
creating part numbers, Design Rules check, Bill of materials, Netlist creation , PCB Layout Design – Building blocks, Component placement,
PCB track routing.
ARM -32 bit Microcontroller family. Architecture of ARM Cortex M3 –General Purpose Registers, Stack Pointer, Link Register, Program
Counter, Special Register,. Nested Vector Interrupt Controller. Interrupt behavior of ARM Cortex M3. Exceptions Programming. Advanced
Programming Features. Memory Protection. Debug Architecture.
Embedded Firmware Design and Development: Embedded Firmware Design Approaches, Embedded Firmware Development Languages
Real-Time Operating System (RTOS) based Embedded System Design: Operating System Basics, Types of OS, Tasks, Process and Threads,
Multiprocessing and Multitasking, Task Scheduling, Threads, Processes and Scheduling: Putting them altogether, Task Communication, Task
Synchronization, Device Drivers, How to Choose an RTOS
The Embedded System Development Environment: The Integrated Development Environment (IDE), Types of Files Generated on Cross
compilation, Disassembler/ELDompiler, Simulators, Emulators and Debugging, Target Hardware Debugging, Boundary Scan.

Reference Books:
1. Shibu K V, “Introduction to Embedded Systems”, Tata McGraw Hill Education Private Limited, 2009
2. Joseph Yiu, “The Definitive Guide to the ARM Cortex-M3”, Newnes, (Elsevier), 2008.
3. James K Peckol, “Embedded Systems – A contemporary Design Tool”, John Weily, 2008.

Digital Circuits and Logic Design
Subject Code : 14ELD14

IA Marks : 50
No. of Lecture Hours /week : 04 Exam Hours : 03
Total no. of Lecture Hours : 50 Exam Marks : 100

Threshold Logic: Introductory Concepts, Synthesis of Threshold Networks
Reliable Design and Fault Diagnosis Hazards: Fault Detection in Combinational Circuits, Fault-Location Experiments, Boolean Differences,
Fault Detection by Path Sensitizing, Detection of Multiple Faults, Failure-Tolerant Design, Quadded Logic
Capabilities, Minimization, and Transformation of Sequential Machines: The Finite- State Model, Further Definitions, Capabilities and
Limitations of Finite – State Machines, State Equivalence and Machine Minimization, Simplification of Incompletely Specified Machines.
Structure of Sequential Machines: Introductory Example, State Assignments Using Partitions, The Lattice of closed Partitions, Reductions of the Output Dependency, Input Independence and Autonomous Clocks, Covers and Generation of closed Partitions by state splitting, Information
Flow in Sequential Machines, ELDompositions, Synthesis of Multiple Machines.
State—Identifications and Fault-Detection Experiments: Homing Experiments, Distinguishing Experiments, Machine Identification, Fault-
Detection Experiments, Design of Diagnosable Machines, Second Algorithm for the Design of Fault Detection Experiments, Fault-Detection
Experiments for Machines which have no Distinguishing Sequences.

Reference Books:
1. Zvi Kohavi, “Switching and Finite Automata Theory”, 2nd Edition. Tata McGraw Hill Edition
2. Charles Roth Jr., “Digital Circuits and logic Design”,
3. Parag K Lala, “Fault Tolerant And Fault Testable Hardware Design”, Prentice Hall Inc. 1985
4. E. V. Krishnamurthy, “Introductory Theory of Computer”, Macmillan Press Ltd, 1983
5. Mishra & Chandrasekaran, “Theory of computer science – Automata, Languages and Computation”, 2nd Edition, PHI,2004

Digital System Design Using Verilog
Subject Code : 14 ELD151

IA Marks : 50
No. of Lecture Hours /week : 04 Exam Hours : 03
Total no. of Lecture Hours : 50 Exam Marks : 100

Introduction and Methodology: Digital Systems and Embedded Systems, Binary representation and Circuit Elements, Real-World Circuits, Models, Design Methodology.
Combinational Basics: Boolean Functions and Boolean Algebra, Binary Coding, Combinational
Components and Circuits, Verification of Combinational Circuits.
Number Basics: Unsigned and Signed Integers, Fixed and Floating-point Numbers.
Sequential Basics: Storage elements, Counters, Sequential Datapaths and Control, Clocked Synchronous Timing Methodology.
Memories: Concepts, Memory Types, Error Detection and Correction.
Implementation Fabrics: ICs, PLDs, Packaging and Circuit Boards, Interconnection and Signal Integrity.
Processor Basics: Embedded Computer Organization, Instruction and Data, Interfacing with memory.
I/O interfacing: I/O devices, I/O controllers, Parallel Buses, Serial Transmission, I/O software.
Accelerators: Concepts, case study, Verification of accelerators.
Design Methodology: Design flow, Design optimization, Design for test.

REFERENCE BOOKS:
1. Peter J. Ashenden, “Digital Design: An Embedded Ssytems Approach UsingVERILOG”, Elesvier, 2010.

Automotive Electronics
Subject Code : 14ELD152

IA Marks : 50
No. of Lecture Hours /week : 04 Exam Hours : 03
Total no. of Lecture Hours : 50 Exam Marks : 100

Automotive Fundamentals Overview – Four Stroke Cycle, Engine Control, Ignition System, Spark plug, Spark pulse generation, Ignition
Timing, Drive Train, Transmission, Brakes, Steering System, Battery, Starting System
Air/Fuel Systems – Fuel Handling, Air Intake System, Air/ Fuel Management
Sensors – Oxygen (O2/EGO) Sensors, Throttle Position Sensor (TPS), Engine Crankshaft Angular Position (CKP) Sensor, Magnetic Reluctance
Position Sensor, Engine Speed Sensor, Ignition Timing Sensor, Hall effect Position Sensor, Shielded Field Sensor, Optical Crankshaft Position
Sensor, Manifold Absolute Pressure (MAP) Sensor – Strain gauge and Capacitor capsule, Engine Coolant Temperature (ECT) Sensor, Intake Air
Temperature (IAT) Sensor, Knock Sensor, Airflow rate sensor, Throttle angle sensor
Actuators – Fuel Metering Actuator, Fuel Injector, Ignition Actuator
Exhaust After-Treatment Systems – AIR, Catalytic Converter, Exhaust Gas Recirculation (EGR), Evaporative Emission Systems
Electronic Engine Control – Engine parameters, variables, Engine Performance terms, Electronic Fuel Control System, Electronic Ignition
control, Idle sped control, EGR Control
Communication – Serial Data, Communication Systems, Protection, Body and Chassis Electrical Systems, Remote Keyless Entry, GPS
Vehicle Motion Control – Cruise Control, Chassis, Power Brakes, Antilock Brake System (ABS), Electronic Steering Control, Power Steering,
Traction Control, Electronically controlled suspension
Automotive Instrumentation – Sampling, Measurement & Signal Conversion of various parameters
Integrated Body – Climate Control Systems, Electronic HVAC Systems, Safety Systems – SIR, Interior Safety, Lighting, Entertainment Systems
Automotive Diagnostics – Timing Light, Engine Analyzer, On-board diagnostics, Off-board diagnostics, Expert Systems
Future Automotive Electronic Systems – Alternative Fuel Engines, Collision Avoidance Radar warning Systems, Low tire pressure warning
system, Radio navigation, Advance Driver Information System

Reference Books:
1. William B. Ribbens, “Understanding Automotive Electronics”, 6th Edition, SAMS/Elsevier Publishing
2. Robert Bosch Gambh, Automotive Electrics Automotive Electronics Systems and Components, 5th edition, John Wiley& Sons Ltd., 2007.

NanoElectronics
Subject Code : 14ELD153

IA Marks : 50
No. of Lecture Hours /week : 04 Exam Hours : 03
Total no. of Lecture Hours : 50 Exam Marks : 100

Introduction: Overview of nanoscience and engineering. Development milestones in microfabrication and electronic industry. Moores law and continued miniaturization., Classification of Nanostructures, Electronic properties of atoms and solids: Isolated atom, Bonding between atoms, Giantmolecular solids, Free electron models and energy bands, crystalline solids, Periodicity of crystal lattices, Electronic conduction, effects of nanometerlength scale, Fabrication methods: Top down processes, Bottom up processes methods for templating the growth of nanomaterials, ordering of nanosystems.
Characterization: Classification, Microscopic techniques, Field ion microscopy, scanning probe techniques, diffraction techniques: bulk,
surface, spectroscopy techniques: photon, radiofrequency, electron, surface analysis and dept profiling: electron, mass, Ion beam,
Reflectrometry, Techniques for property measurement: mechanical, electron, magnetic, thermal properties.
Inorganic semiconductor nanostructures: overview of semiconductor physics. Quantum confinement in semiconductor nanostructures:
quantumwells, quantum wires, quantum dots, super-lattices, band offsets, electronicdensity of states.
Fabrication techniques: requirements of ideal semiconductor, epitaxial growth of quantum wells, lithography and etching, cleaved edgeover
growth, growth of vicinal substrates, strain induced dots and wires, electrostatically induced dots and wires, Quantum well width fluctuations,
thermally annealed quantum wells, semiconductor nanocrystals, collidal quantum dots, self-assembly techniques.
Physical processes: modulation doping, quantum hall effect, resonanttunneling, charging effects, ballistic carrier transport, Inter band
absorption, intraband absorption, Light emission processes, phonon bottleneck, quantumconfined stark effect, nonlinear effects, coherence and
dephasing, characterization of semiconductor nanostructures: optical electrical and structural.
Methods of measuring properties-structure:atomic,crystallography,microscopy,spectroscopy. Properties of nanoparticles: metalnano clusters,
semiconducting nanoparticles, rare gas and molecularclusters, methods of synthesis(RF, chemical, thermolysis, pulsed laser methods) Carbon
nanostructures and its applications(field emission and shielding, computers, fuelcells, sensors, catalysis).Self assembling nanostructured
molecular materials and devices: building blocks, principles of self assembly, methods to prepare and pattern nanoparticles, template
dnanostructures, liquid crystal mesophases. Nanomagnetic materials and devices: magnetism, materials, magnetoresistance, nanomagnetism
intechnology, challenges facing nanomagnetism.
Applications: Injectionlasers, quantumcascadelasers, singlephotonsources, biologicaltagging, opticalmemories, coulomb blockade devices,
photonic structures, QWIP’s, NEMS, MEMS.

Reference Books:
1. Ed Robert Kelsall,IanHamley,MarkGeoghegan, “ Nanoscale science and technology” ,John wiley and sons,2007.
2. Charles P Poole,Jr,Frank J owens, “Introduction to Nanotechnology” ,John wiley,copyright 2006,Reprint 2011.
3. Ed William A Goddard III,Donald W Brenner,Sergey EdwardLyshevski,Gerald J Lafrate, “ Hand Book of Nanoscience Engineering and Technology” ,CRC press,2003

ASIC Design
Subject Code : 14EVE154

IA Marks : 50
No. of Lecture Hours /week : 04 Exam Hours : 03
Total no. of Lecture Hours : 50 Exam Marks : 100

Note: All Designs Will Be Based On VHDL

Introduction: Full Custom with ASIC, Semi custom ASICS, Standard Cell based ASIC, Gate array based ASIC, Channelled gate array, Channel
less gate array, structured get array, Programmable logic device, FPGA design flow, SIC cell libraries.
Data Logic Cells: Data Path Elements, Adders, Multiplier, Arithmetic Operator, I/O cell, Cell Compilers
ASIC Library Design: Logical effort: practicing delay, logical area and logical efficiency logical paths, multi stage cells, optimum delay,
optimum no. of stages, library cell design.
Low-Level Design Entry: Schematic Entry: Hierarchical design. The cell library, Names, Schematic, Icons & Symbols, Nets, schematic entry
for ASIC’S, connections, vectored instances and buses, Edit in place attributes, Netlist, screener, Back annotation.
Programmable ASIC: programmable ASIC logic cell, ASIC I/O cell.
A Brief Introduction to Low Level Design Language: an introduction to EDIF, PLA Tools, an introduction to CFI designs representation. Half
gate ASIC. Introduction to Synthesis and Simulation.
ASIC Construction Floor Planning and Placement And Routing: Physical Design, CAD Tools, System Partitioning, Estimating ASIC size,
partitioning methods. Floor planning tools, I/O and power planning, clock planning, placement algorithms, iterative placement improvement,
Time driven placement methods. Physical Design flow global Routing, Local Routing, Detail Routing, Special Routing, Circuit Extraction and DRC.

Reference Books:
1. M.J.S .Smith, “Application – Specific Integrated Circuits”, Pearson Education, 2003.
2. Jose E.France, YannisTsividis, “Design of Analog-Digital VLSICircuits for Telecommunication and signal processing”, Prentice Hall, 1994.
3. MalcolmR.Haskard; Lan. C. May, “Analog VLSI Design – NMOSand CMOS”, Prentice Hall, 1998.
4. Mohammed Ismail and Terri Fiez, “Analog VLSI Signal andInformation Processing”, McGraw Hill, 1994.

Advanced Mathematics
Subject Code : 14ELD11

IA Marks : 50
No. of Lecture Hours / Week : 04 Exam. Hours : 03
Total No. of Lecture Hours : 50 Exam. Marks : 100

Matrix Theory
QR EL Decomposition – Eigen values using shifted QR algorithm- Singular Value EL Decomposition – Pseudo inverse- Least square approximations
Calculus of Variations
Concept of Functionals- Euler’s equation – functional dependent on first and higher order derivatives – Functionals on several dependent variables – Iso perimetric problems- Variational problems with moving boundaries
Transform Methods
Laplace transform methods for one dimensional wave equation – Displacements in a string – Longitudinal vibration of a elastic bar – Fourier transform methods for one dimensional heat conduction problems in infinite and semi infinite rod.
Elliptic Equation
Laplace equation – Properties of harmonic functions – Fourier transform methods for laplace equations. Solution for Poisson equation by Fourier transforms method
Linear and Non Linear Programming
Simplex Algorithm- Two Phase and Big M techniques – Duality theory- Dual Simplex method. Non Linear Programming –Constrained extremal problems- Lagranges multiplier method- Kuhn- Tucker conditions and solutions

Reference Books:
1. Richard Bronson, “Schaum’s Outlines of Theory and Problems of Matrix Operations”, McGraw-Hill, 1988.
2. Venkataraman M K, “Higher Engineering Mathematics”, National Pub. Co, 1992.
3. Elsgolts, L., “Differential Equations and Calculus of Variations”, Mir, 1977.
4. Sneddon,I.N., “Elements of Partial differential equations”, Dover Publications, 2006.
5. Sankara Rao, K., “Introduction to partial differential equations”, Prentice – Hall of India, 1995
6. Taha H A, “Operations research – An introduction”, McMilan Publishing co, 1982.

Digital Electronics Lab -1
Subject Code : 14ELD16

IA Marks : 25
No. of Lecture Hours /week : 03 Exam Hours : 03
Total no. of Lecture Hours : 42 Exam Marks : 50

Design Using Cadence ORCAD
1. Design of 3½ Digit Digital Voltmeter
2. Design of Monolithic function Generator.
3. Design of Regulator Power supplies.
4. Design of Batch counter using TTL ICs.
5. Design of DAC and ADC.
6. Design of Electronic P, PI, PID and ON/OFF controllers.
7. Design of Programmable Timers.
8. Design of filters and resonance circuits.

VLSI DIGITAL DESIGN
FPGA DIGITAL DESIGN
VLSI Front End Design programs:

Programming can be done using any complier. Down load the programs on FPGA/CPLD boards and performance testing may be done using
pattern generator (32 channels and logic analyzer )/Chipscope pro apart from verification by simulation with any of the front end tools
1. Write Verilog code for the design of 8-bit
i. Carry Ripple Adder
ii. Carry LookAhead adder
iii. Carry Skip Adder
iv. BCD Adder &Subtracter

2. Write Verilog Code for 8-bit
i. Array Multiplication (Signed and Unsigned)
ii. Booth Multiplication (Radix-4)

3. Write Verilog code for 4/8-bit
i. Magnitude Comparator
ii. LFSR
iii.Parity Generator
iv.Universal Shift Register

4. Write Verilog Code for 3-bit Arbitary Counter to generate 0,1,2,3,6,5,7 and repeats.

5. Design a Mealy and Moore Sequence Detector using Verilog to detect Sequence.
Eg 11101 (with and without overlap) any sequence can be specified

6. Design a FIFO and LIFO buffers in Verilog and Verify its Operation.

7. Design a coin operated public Telephone unit using Mealy FSM model with following operations
i. The calling process is initiated by lifting the receiver.
ii. Insert 1 Rupee Coin to make a call.
iii. If line is busy, placing the receiver on hook should return a coin
iv. If line is through, the call is allowed for 60 seconds at the 45th second prompt another 1 Rupee coin to be inserted, to continue the call.
v. If user doesn’t insert the coin within 60 seconds the call should be terminated.
vi. The system is ready to accept new call request when the receiver is placed on the hook.
vii. The FSM goes ‘out of order’ state when there is a Line Fault.

Note: Implementing the above designs on Xilinx/Altera/Cypress/equivalent based FPGA/CPLD kits

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