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Unit 1, MOSFETS, Unit 5, Feedback Amplifiers and Unit 6, Operational Amplifiers
Prof. S V Uma
Unit 2, Single stage IC Amplifier, Unit 3, Single Stage IC Amplifiers and Unit 4, Single Stage IC Amplifiers
Prof. Prakash Tunga
Unit 7 & 8, Digital CMOS Circuits
Prof. Shylashree N
Notes Credits – VTU ELearning
Unit 1 – Sample Notes
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MOS Field-Effect Transistors (MOSFETs)
UNIT 1 OUTLINE
1.1 Device Structure and Physical Operation
1.2 Current – Voltage Characteristics
1.3 MOSFET Circuits at DC
1.4 Biasing in MOS amplifier circuits
1.5 Small Signal Operation and Models
1.6 The MOSFET as an Amplifier and as a Switch
1.7 Single Stage MOS amplifiers
1.8 SPICE MOSFET models and examples
At the end of this chapter one can clearly get to know the following:
- Understanding Physical construction and operation of an Enhancement MOSFET
- Drawing the V-I characteristics of n and p channel E-MOSFET
- DC operation or biasing of MOSFETs
- AC Operation: Small signal modeling of MOSFETs
- Single stage MOS amplifiers : Common Source, Common Drain and Common Gate amplifiers
- SPICE modeling of MOSFETs
Along with the Junction Field Effect Transistor (JFET), there is another type of Field Effect Transistor available whose Gate input is electrically insulated from the main current carrying channel and is therefore called an Insulated Gate Field Effect Transistor or IGFET. The most common type of insulated gate FET which is used in many different types of electronic circuits is called the Metal Oxide Semiconductor Field Effect Transistor or MOSFET for short.
The IGFET or MOSFET is a voltage controlled field effect transistor that differs from a JFET in that it has a “Metal Oxide” Gate electrode which is electrically insulated from the main semiconductor N-channel or P-channel by a thin layer of insulating material usually silicon dioxide (commonly known as glass). This insulated metal gate electrode can be thought of as one plate of a capacitor. The isolation of the controlling Gate makes the input resistance of the MOSFET extremely high in the Mega-ohms (MΩ) region thereby making it almost infinite.
As the Gate terminal is isolated from the main current carrying channel “NO current flows into the gate” and just like the JFET, the MOSFET also acts like a voltage controlled resistor were the current flowing through the main channel between the Drain and Source is proportional to the input voltage. Also like the JFET, this very high input resistance can easily accumulate large amounts of static charge resulting in the MOSFET becoming easily damaged unless carefully handled or protected.
MOSFETs are three terminal devices with a Gate, Drain and Source and both P-channel (PMOS) and N-channel (NMOS) MOSFETs are available. The main difference this time is that MOSFETs are available in two basic forms:
1. Depletion Type – the transistor requires the Gate-Source voltage, (VGS) to switch the device “OFF”. The depletion mode MOSFET is equivalent to a “Normally Closed” switch.
2. Enhancement Type – the transistor requires a Gate-Source voltage, (VGS) to switch the device “ON”. The enhancement mode MOSFET is equivalent to a “Normally Open” switch.
Basic operating principle of a MOSFET:
Use of the voltage between two terminals to control the current flowing in the third terminal
Also, the control signal can be used to cause the current in the third terminal to change from zero to a large value, thus allowing the device to act as a switch.
The FET differs from BJT in the following important characteristics:
1. It is a unipolar device
2. It is simpler to fabricate
3. Occupies less space in Integrated form, packaging density is high(>200 million)
4. It has higher input resistance
5. It can be used as a symmetrical Bilateral switch
6. It functions as a memory device
7. It is less noisy than a BJT
8. It exhibits no offset voltage at zero input, hence making an excellent signal chopper
THE ONLY DISADVANTAGE IS IT HAS SMALLER GAIN- BANDWIDTH PRODUCT THAN BJT
The symbols and basic construction for both configurations of MOSFETs are shown below.
[Refer PDF File]
Figure 4.1 shows the physical structure of the n-channel enhancement-type MOSFET. The transistor is fabricated on a p-type substrate. Two heavily doped n-type regions: the n+ source and the n+ drain regions, are created in the substrate.
Figure 1. Physical structure of the enhancement-type NMOS transistor: (a)Perspective view; (b)Cross-section. Typically L= 0.1 to 3 μm, W= 0.2 to 100 μm, and the thickness of the oxide layer (tox) is in the range of 2 to 50 nm.
1. A thin layer of silicon dioxide (SiO2) of thickness tox (typically 2-50 nm) – an excellent electrical insulator, is grown on the surface of the substrate, in the area between the source and drain regions.
2. Metal is deposited on top of the oxide layer to form the gate electrode.
3. Metal contacts are also made to the source region, the drain region, and the substrate, also known as the body.
Thus four terminals are brought out: the gate terminal (G), the source terminal (S), the drain terminal (D), and the substrate or body terminal (B).
A voltage applied to the gate of the MOSFET controls current flow between source and drain. This current will flow in the longitudinal direction from drain to source in the region labelled “channel region.”
This region has a length L in the range of 0.1 μm to 3 μm, and a width W in the range of 0.2 μm to 100 μm.
Note: The MOSFET is a symmetrical device [its source and drain can be interchanged with no change in device characteristics].
(i) With No Gate Voltage
With no bias voltage applied to the gate, two back-to-back diodes exist in series between drain and source. They prevent current conduction from drain to source when a voltage VDS is applied. The path between drain and source has a very high resistance (of the order of 1012Ω).
(ii) Creating a Channel for Current Flow
The source and the drain are grounded and a positive voltage is applied to the gate. The positive voltage on the gate causes the free holes (which are positive charged) to be repelled from the region of the substrate under the gate. These holes are pushed downward into the substrate, leaving behind a carrier-depletion region as shown below.
The positive gate voltage attracts electrons from the n+ source and drain regions into the channel region. When a sufficient number of electrons accumulate near the surface of the substrate under the gate, an n region is in effect created, connecting the source and drain regions, as indicated in Fig. 4.2. This MOSFET is called an n-channel MOSFET or, alternatively, an NMOS transistor. The induced channel is also called an inversion layer. The induced n region thus forms a channel for current flow from drain to source.
Note: The value of VGS at which a sufficient number of mobile electrons accumulate in the channel region to form a conducting channel is called the threshold voltage and is denoted Vt.
Figure 4.2 The enhancement-type NMOS transistor with a positive voltage applied to the gate. An n channel is induced at the top of the substrate beneath the gate.
The value of Vt is controlled during device fabrication and typically lies in the range of 0.5 V to 1.0V.
Now if a voltage is applied between drain and source, current flows through this induced n region.
[Refer PDF File for Complete Notes ]
Unit 2: Integrated-circuit amplifiers- sAMPLE nOTES
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This chapter begins with a brief discussion on the design philosophy of integrated circuits, and how it differs from that of discrete circuits. Next is the comparison of MOS & BJT in terms of their parameters, characteristics and models. This is followed by current mirror circuits and steering circuits. These circuits are realized using both MOS and BJTs. The chapter ends with general considerations in high frequency response of amplifiers.
IC DESIGN PHOLOSOPHY
Integrated-circuit fabrication technology poses constraints on-and provides opportunities to- the circuit designer. Thus, while chip-area considerations dictate that large-and even moderate-value resistors are to be avoided, constant-current sources are readily available. Large capacitors, for signal coupling and bypass, are not to be used, except perhaps as components external to the IC chip. Even then, the number of such capacitors has to be kept to a minimum; otherwise the number of pin terminals and hence its cost increase. Very small capacitors, in the picofarad and fraction of picofarad range, however, are easy to fabricate in IC MOS technology and can be combined with MOS amplifiers and MOS switches to realize a wide range of signal processing functions, both analog and digital.
As a general rule, in designing IC MOS circuits, one should strive to realize as many of the functions required as possible using MOS transistors only and, when needed, small MOS capacitors. MOS transistor can be sized; that is, their W and L values can be selected, to fit a wide range of requirements. To pack a larger number of devices on the same IC chip, the trend has been to reduce the device dimensions. CMOS process technologies capable of producing devices with a 0.1μm minimum channel length are in use. Such small devices need operate with dc voltage supplies close to 1V. While lowvoltage operation can help to reduce power dissipation, it poses lot of challenges to the circuit designer. For example, such MOS transistors must be operated overdrive voltages of only 0.2V or so.
The MOS-amplifier circuits that we shall study will be designed almost entirely using MOSFETs of both polarities-that is, NMOS and PMOS.They are readily available in CMOS process technology. As mentioned earlier, CMOS is currently the most widely used IC technology for both analog and digital as well as combined analog and digital(or mixed-signal)applications. Nevertheless, bipolar integrated circuit still offer many exciting opportunities to the analog design engineer. This is especially the case for general-purpose circuit packages, such as high-quality op amps that are intended for assembly on printed-circuit(pc) board. As well, bipolar circuits can provide much higher output currents and are favoured for certain applications, such as in the automotive industry, for their high reliability under severe environment conditions. Finally, bipolar circuits can be combined with CMOS in innovative and exciting ways.
Introduction to MOSFET Scaling
In 1965, G.E. Moore predicted that the number of transistors in ICs would double after every two years. This prediction has come true and today’s Pentium processor accommodates approximately 14.2million transistors in 1.7 x 2 cm2.The only way to assemble a large number of transistors in given silicon area is to reduce the size of the transistor. The process of reducing vertical and horizontal dimensions of MOSFETs is called scaling. In order to meet Moore’s law, the channel length (L) and width (W) of the MOSFET are reduced by a factor 0.7. If we reduce by a factor of 0.7, the area of the MOSFET, which is W X L, reduces by half. Hence, in the given area we can assemble double the number of transistors.
Scaling is defined as the process of reducing the horizontal and vertical dimensions of a MOS device by some scaling factor S, which is greater than 1. Thus, the scaled device is obtained by simply dividing the key dimensions of the MOSFET such as channel length (L), channel width (W),oxide thickness(tox), and junction depth (Xj),by scaling factor S. MOSFET scaling offers several benefits such as increased component density, increase speed, reduction in power consumption, and cost per chip. Two type of schemes commonly used for MOSFET scaling are constant –voltage scaling are constant-field scaling.
Constant –Field Scaling: In constant-field scaling, the MOSFET dimensions as well as supply voltages are scaled by the same scaling factor S, greater than 1.The scaling of supply and terminal voltage maintains the same electric field as that of original device; hence such scaling is termed constant-field scaling. Such scaling is also called full scaling, as the geometric dimensions and supply voltages are scaled simultaneously. In order to maintain charge and electric field relationship, the doping densities are scaled by scaling factor S. Constant scaling offers benefits such as increased component density, increased speed, decreased cost, etc. The impact of constant-field scaling on the physical parameters of the MOSFET is summarized in below table.
[Refer PDF File]